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15 kv esd protected, slew rate limited, 5 v, rs-485 transceiver adm483e rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?1997C2007 analog devices, inc. all rights reserved. features 15 kv esd protection 250 kbps data rate reduced slew rate for low em interference single 5 v 10% supply ?7 v to +12 v bus common-mode range up to 32 nodes on the bus receiver open-circuit, fail-safe design short-circuit protection 36 a supply current 0.1 a shutdown current applications low power rs-485 systems electrically harsh environments emi sensitive applications dte-dce interface packet switching local area networks functional block diagram r d adm483e b a ro re de di 0 6012-001 figure 1. general description the adm483e is a 5 v, low power data transceiver with 15 kv esd protection suitable for half-duplex communication on multipoint bus transmission lines. the adm483e is designed for balanced data transmission and complies with tia/eia standards rs-485 and rs-422, which allow up to 32 transceivers on a bus. the adm483e has a low current shutdown mode in which it consumes only 0.1 a. because only one driver is enabled at any time, the output of a disabled or power-down driver is three-stated to avoid overloading the bus. drivers are short-circuit current-limited and are protected against excessive power dissipation by thermal shutdown circuitry that places their outputs into a high impedance state. the receiver input has a fail-safe feature that guarantees a logic high output if the input is open circuit. the adm483e is fully specified over the industrial temperature ranges and is available in 8-lead soic_n packages.
adm483e rev. a | page 2 of 16 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing specifications .................................................................. 4 absolute maximum ratings............................................................ 5 esd caution.................................................................................. 5 pin configuration and function descriptions............................. 6 typical performance characteristics ............................................. 7 test circuits and switching characteristics...................................9 general information ...................................................................... 11 esd transient protection scheme ........................................... 11 esd testing ................................................................................. 12 applications information .............................................................. 13 differential data transmission ................................................ 13 cable and data rate................................................................... 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 12/07rev. 0 to rev. a updated format..................................................................universal changes to features ......................................................................... 1 changes to general description .................................................... 1 changes to table 1............................................................................ 3 changes to table 2............................................................................ 4 changes to table 3............................................................................ 5 changes to table 5............................................................................ 6 changes to typical performance characteristics section........... 7 changes to test circuits and switching characteristics section...9 changes to general information section.................................... 11 updated outline dimensions ....................................................... 14 changes to ordering guide .......................................................... 14 1/97revision 0: initial version
adm483e rev. a | page 3 of 16 specifications v cc = 5 v 10%. all specifications t min to t max , unless otherwise noted. table 1. parameter min typ max unit test conditions/comments driver differential output voltage, v od 5.0 v v cc = 5.25 v; r = , see figure 15 2.0 5.0 v r = 50 (rs-422), see figure 15 1.5 5.0 v r = 27 (rs-485), see figure 15 1.5 5.0 v v in = C7 v to +12 v |v od | for complementary output states 0.2 v r = 27 or 50 , see figure 15 common-mode output voltage, v oc 3 v r = 27 or 50 , see figure 15 |v oc | for complementary output states 0.2 v r = 27 or 50 output short-circuit current (v out = high) 250 ma C7 v v o +12 v output short-circuit current (v out = low) 250 ma C7 v v o +12 v cmos input logic threshold low, v inl 1.4 0.8 v cmos input logic threshold high, v inh 2.0 1.4 v logic input current (de, di) 1.0 a receiver differential input threshold voltage, v th ?0.2 +0.2 v ?7 v v cm +12 v input voltage hysteresis, v th 70 mv v cm = 0 v input resistance 12 k ?7 v v cm +12 v input current (a, b) 1 ma v in = 12 v ?0.8 ma v in = C7 v logic enable input current ( re ) 1 a cmos output voltage low, v ol 0.4 v i out = 4.0 ma cmos output voltage high, v oh 4.0 v i out = ?4.0 ma short-circuit output current 7 85 ma v out = gnd or v cc three-state output leakage current 2.0 a 0.4 v v out 2.4 v power supply current outputs unloaded, receivers enabled i cc 36 120 a de = 0 v (disabled), re = 0 v 270 360 a de = 5 v (enabled), re = 0 v supply current in shutdown 0.1 10 a de = 0 v, re = v cc esd immunity esd protection 15 kv hbm air discharge; pin a, pin b
adm483e rev. a | page 4 of 16 timing specifications v cc = 5 v 10%. all specifications t min to t max , unless otherwise noted. table 2. parameter min typ max unit test conditions/comments driver propagation delay input to output (t plh , t phl ) 250 2000 ns r l diff = 54 , c l1 = c l2 = 100 pf, see figure 16 and figure 17 driver output to output (t skew ) 100 800 ns r l diff = 54 , c l1 = c l2 = 100 pf, see figure 16 and figure 17 driver rise/fall time (t r , t f ) 250 2000 ns r l diff = 54 , c l1 = c l2 = 100 pf, see figure 16 and figure 17 driver enable to output valid 250 2000 ns r l = 500 , c l = 100 pf, see figure 18 and figure 19 driver disable timing 300 3000 ns r l = 500 , c l = 15 pf, see figure 18 and figure 19 receiver propagation delay input to output (t plh , t phl ) 250 2000 ns c l = 15 pf, see figure 20 skew (|t plh C t phl |) 200 ns receiver enable (t en1 ) 10 50 ns r l = 1 k, c l = 15 pf, see figure 22 receiver disable (t en2 ) 10 50 ns r l = 1 k, c l = 15 pf, see figure 22 shutdown time to shutdown 50 200 3000 ns driver enable from shutdown 5000 ns r l = 500 , c l = 100 pf, see figure 18 and figure 19 receiver enable from shutdown 5000 ns r l = 1 k, c l = 15 pf, see figure 22
adm483e rev. a | page 5 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v cc to gnd ?0.5 v to +6 v digital i/o voltage (de, re ) ?0.5 v to (v cc + 0.5 v) driver input voltage (di) ?0.5 v to (v cc + 0.5 v) receiver output voltage (ro) ?0.5 v to (v cc + 0.5 v) driver output/receiver input voltage (pin a, pin b) ?9 v to +14 v esd rating: air (human body model) (pin a, pin b) 15 kv power dissipation 8-lead soic_n 470 mw ja , thermal impedance 110c/w operating temperature range industrial (a version) ?40c to +85c storage temperature range ?65c to +150c lead temperature (soldering, 10 sec) 300c vapor phase (60 sec) 215c infrared (15 sec) 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adm483e rev. a | page 6 of 16 pin configuration and fu nction descriptions ro 1 re 2 de 3 di 4 v cc 8 b 7 a 6 gnd 5 adm483e top view (not to scale) 0 6012-002 figure 2. pin configuration table 4. pin function descriptions pin o. mnemonic description 1 ro receiver output. when enabled, if a > b by 200 mv, then ro = high. if a < b by 200 mv, then ro = low. 2 re receiver output enable. a low level enables the receiver output, ro. a high level places the receiver output in a high impedance state. 3 de driver output enable. a high level enables the driver differential outputs, a and b. a low level places the driver differential outputs in a high impedance state. 4 di driver input. when the driver is enabled, a logic low on di forces a low and b high. a logic high on di forces a high and b low. 5 gnd ground connection, 0 v. 6 a noninverting receiver input a/driver output a. 7 b inverting receiver input b/driver output b. 8 v cc power supply, 5 v 10%. table 5. selection table part o. duple data rate bps o poer shuton t/r enable i a o. o t/r on us esd v adm483e half 250 yes yes 36 32 15
adm483e rev. a | page 7 of 16 typical performance characteristics 0 5 10 15 20 25 30 35 40 45 50 0 0.5 1.0 1.5 2.0 2.5 output low voltage (v) output current (ma) 06012-003 figure 3. output current vs. receiver output low voltage ? 30 ?25 ?20 ?15 ?10 ?5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output high voltage (v) output current (ma) 0 6012-004 figure 4. output current vs. receiver output high voltage 3.9 4.0 4.1 4.2 4.3 4.4 4.5 ?40 ?20 0 20 40 60 80 temperature (c) output high voltage (v) 06012-005 figure 5. receiver output high voltage vs. temperature 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 ?40 ?20 0 20 40 60 80 temperature (c) output low voltage (v) 06012-006 figure 6. receiver output low voltage vs. temperature 0 5 10 15 20 25 30 35 40 45 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 differential output voltage (v) o u t p u t c u r r e n t ( m a ) 06012-007 figure 7. driver output current vs. differential output voltage 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 ?40?200 20406080 temperature (c) differential output voltage (v) 06012-008 figure 8. driver differential output voltage vs. temperature
adm483e rev. a | page 8 of 16 0 20 40 60 80 100 120 140 024681012 output low voltage (v) output current (ma) 06012-009 figure 9. output current vs . driver output low voltage ? 140 ?120 ?100 ?80 ?60 ?40 ?20 0 ?8 ?6 ?4 ?2 0 2 4 6 output high voltage (v) output current (ma) 06012-010 figure 10. output current vs. driver output high voltage 0 100 200 300 400 500 600 ?40 ?20 0 20 40 60 80 temperature (c) supply current (a) de = v cc and re = x de = 0 and re = 0 de = 0 and re = v cc 06012-011 figure 11. adm483e supply current vs. temperature 0 1 2 3 4 5 6 7 8 9 10 ?60 ?40 ?20 0 20 40 60 80 100 temperature (c) shutdown current (a) 06012-012 figure 12. shutdown current vs. temperature ch1 5.00v ch3 500mv ch2 500mv m200ns a ch1 2.80v t 57.60% ro b a 1 2 0 6012-013 figure 13. adm483e receiver t phl ch1 5.00v ch3 500mv ch2 500mv m200ns a ch1 2.80v 1 t 60.80% ro a b 2 06012-014 figure 14. adm483e receiver t plh driven by external rs-485 device
adm483e rev. a | page 9 of 16 test circuits and switching characteristics z y v od v oc r l r l 0 6012-015 figure 15. driver dc test load di de 5 v a b r l c l c l v od 06012-016 figure 16. driver timing test circuit 5 v 1.5v 1/2v o 10% 90% 90% 10% di a b 0v 0v +v o v o ?v o v diff t skew = t dplh ? t dphl v diff = v (a) ? v (b) t dr t dplh t dphl t df 1/2 v o 06012-017 figure 17. driver propagation delays generator 0 or 5v 50? r l = 500 ? out c l s1 1.5v 5v 0v v oh 0v 0.5v 2.3v out de t dhz t dzh, t dzh(shdn) d 06012-018 figure 18. driver enable and disable times (t dhz , t dzh , t dzh(shdn) ) generator 0v or 5v 50? d r l = 500 ? v cc out c l s1 v cc /2 5v 0v 0.5v 2.3v v ol out v cc de t dlz t dzl, t dzl(shdn) 0 6012-019 figure 19. driver enable and disable times (t dzl , t dlz , t dzl(shdn) ) ate b receiver output a r v id 06012-020 figure 20. receiver propagation delay test circuit the rise time and fall time of input a and input b < 4ns +1v ?1v t rphl t rplh 1.5v b ro v oh v ol a 06012-021 figure 21. receiver propagation delays
adm483e rev. a | page 10 of 16 generator +1.5v ?1.5v 0v or 5v re ro 50 ? s1 s2 t rzh, t rzh(shdn) t rhz +5v 0v 0v v oh +1.5v +1.5v +0.5v s1 open s2 closed s3 = +1.5v re ro t rzl, t rzl(shdn) +5v 0v v cc v ol +1.5v +1.5v re ro +5v 0v 0v v oh s1 open s2 closed s3 = +1.5v s1 closed s2 open s3 = ?1.5v t rlz +1.5v +0.5v re ro +5v 0v v cc v ol s1 closed s2 open s3 = +1.5v s3 v id 1k ? c l 15pf v cc 06012-022 figure 22. receiver enable and disable times
adm483e rev. a | page 11 of 16 general information the adm483e is a robust rs-485 transceiver that operates from a single 5 v supply. it is ideally suited for operation in electrically harsh environ- ments or where cables may be plugged and unplugged. it is also immune to high rf field strengths without special shielding precautions. the adm483e is intended for balanced data transmission and complies with both eia standards rs-485 and rs-422. it contains a differential line driver and a differential line receiver; it is suitable for half-duplex data transmission because the driver and receiver share the same differential pins. the input impedance on the adm483e is 12 k, allowing up to 32 transceivers on the differential bus. the adm483e operates from a single 5 v 10% power supply. excessive power dissipation caused by bus contention or by output shorting is prevented by a thermal shutdown circuit. this feature forces the driver output into a high impedance state if, during fault conditions, a significant temperature increase is detected in the internal driver circuitry. the receiver has a fail-safe feature that results in a logic high output state if the inputs are unconnected (floating). a high level of robustness is achieved using internal protection circuitry, eliminating the need for external protection components such as transorbs or surge suppressors. low electromagnetic emissions are achieved using slew limited drivers, minimizing interference both conducted and radiated. the adm483e can transmit at data rates up to 250 kbps. a typical application for the adm483e is illustrated in figure 23 . this figure shows a half-duplex link where data may be transferred at rates up to 250 kbps. a terminating resistor is shown at both ends of the link. this termination is not critical because the slew rate is controlled by the adm483e and reflections are minimized. the communications network can be extended to include multipoint connections as shown in figure 26 . up to 32 transceivers can be connected to the bus. e384mda e384mda rs-485/rs-422 link ro di de di de b a gnd b a gnd ro 0.1f 0.1f +5 v +5 v v cc v cc re re 06012-023 figure 23. typical half-duplex link application table 6 and table 7 show the truth tables for transmitting and receiving. table 6. transmitting truth table inputs utputs re de di a x 1 1 1 0 1 x 1 1 0 1 0 0 0 x 1 high-z high-z 1 0 x 1 high-z high-z 1 x = dont care. table 7. receiving truth table inputs utputs re de a r 0 0 +0.2 v 1 0 0 ?0.2 v 0 0 0 inputs o/c 1 1 0 x 1 high-z 1 x = dont care. esd transient protection scheme the adm483e uses protective clamping structures on its inputs and outputs that clamp the voltage to a safe level and dissipate the energy present in esd (electrostatic discharge). the protection structure achieves esd protection up to 15 kv according to the human body model.
adm483e rev. a | page 12 of 16 esd testing two coupling methods are used for esd testing: contact discharge and air-gap discharge. contact discharge calls for a direct connection to the unit being tested. air-gap discharge uses a higher test voltage but does not make direct contact with the unit under test. with air-gap discharge, the discharge gun is moved toward the unit under test, developing an arc across the air gap. this method is influenced by humidity, temperature, barometric pressure, distance, and rate of closure of the discharge gun. the contact discharge method, though less realistic, is more repeatable and is gaining acceptance and preference over the air-gap method. although very little energy is contained within an esd pulse, the extremely fast rise time, coupled with high voltages, can cause failures in unprotected semiconductors. catastrophic destruction may occur immediately as a result of arcing or heating. even if catastrophic failure does not occur immediately, the device may suffer from parametric degradation, which can result in degraded performance. the cumulative effects of continuous exposure may eventually lead to complete failure. c1 r2 high voltage generator device under test esd test method human body model r2 1.5k ? c1 100pf 06012-024 figure 24. esd generator i/o lines are particularly vulnerable to esd damage. simply touching or plugging in an i/o cable can result in a static discharge that may damage or completely destroy the interface product connected to the i/o port. it is, therefore, extremely important to have high levels of esd protection on the i/o lines. it is possible that the esd discharge could induce latch-up in the device under test. therefore, it is important that esd testing on the i/o pins be carried out while device power is applied. this type of testing is more representative of a real-world i/o discharge where the equipment is operating normally when the discharge occurs. 100% 90% 36.8% 10% time ( t ) i peak t rl t dl 06012-025 figure 25. human body model esd current waveform table 8. adm483e esd test results esd test method i/o pins human body model: air 15 kv human body model: contact 8 kv
adm483e rev. a | page 13 of 16 applications information differential data transmission differential data transmission is used to reliably transmit data at high rates over long distances and through noisy environments. differential transmission nullifies the effects of ground shifts and noise signals that appear as common-mode voltages on the line. there are two main standards approved by the electronics industries association (eia) that specify the electrical character- istics of transceivers used in differential data transmission. the rs-422 standard specifies data rates up to 10 mbaud and line lengths up to 4000 feet. a single driver can drive a transmission line with up to 10 receivers. to accommodate true multipoint communications, the rs-485 standard was defined. this standard meets or exceeds all the requirements of rs-422 and also allows for up to 32 drivers and 32 receivers to be connected to a single bus. an extended common-mode range of ?7 v to +12 v is defined. the most significant difference between rs-422 and rs-485 is the fact that the drivers can be disabled, thereby allowing more than one (32, in fact) to be connected to a single line. only one driver should be enabled at a time, but the rs-485 standard contains additional specifications to guarantee device safety in the event of line contention. cable and data rate the transmission line of choice for rs-485 communications is a twisted pair. twisted pair cable tends to cancel common-mode noise and also cancels the magnetic fields generated by the current flowing through each wire, thereby reducing the effective inductance of the pair. a typical application showing a multipoint transmission network is shown in figure 26 . an rs-485 transmission line can have as many as 32 transceivers on the bus. only one driver can transmit at a particular time, but multiple receivers can be enabled simultaneously. d r d rr r d d rt rt 06012-026 figure 26. typical rs-485 network
adm483e rev. a | page 14 of 16 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-a a 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 27. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) ordering guide model temperature range package descript ion package option ordering quantity adm483ear C40c to +85c 8-lead standard small outline package (soic_n) r-8 ADM483EAR-REEL C40c to +85c 8-lead standard small outline package (soic_n) r-8 2500 adm483earz 1 C40c to +85c 8-lead standard small outline package (soic_n) r-8 adm483earz-reel 1 C40c to +85c 8-lead standard small outline package (soic_n) r-8 2500 1 z = rohs compliant part.
adm483e rev. a | page 15 of 16 notes
adm483e rev. a | page 16 of 16 notes ?1997C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06012-0-12/07(a)

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